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-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.

-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "03/15/2020 23:24:54"

-- Vhdl Test Bench template for design  :  ejemplo
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ejemplo_vhd_tst is
end ejemplo_vhd_tst;



architecture ejemplo_arch of ejemplo_vhd_tst is
-- constants                              
  constant clock_period : time := 100 ns;
  constant reset_time   : time := clock_period*2.5;
  constant delay        : time := 10 ns;  -- desfasaje de reloj

-- signals                                                    
  signal A    : std_logic_vector(7 downto 0);
  signal B    : std_logic_vector(7 downto 0);
  signal clk  : std_logic;
  signal ena  : std_logic;
  signal rstn : std_logic;
  signal S    : std_logic_vector(7 downto 0);

  component ejemplo
    port (
      A    : in  std_logic_vector(7 downto 0);
      B    : in  std_logic_vector(7 downto 0);
      clk  : in  std_logic;
      ena  : in  std_logic;
      rstn : in  std_logic;
      S    : out std_logic_vector(7 downto 0)
      );
  end component;
  
begin
  DUT : ejemplo
    port map (
-- list connections between master ports and signals
      A    => A,
      B    => B,
      clk  => clk,
      ena  => ena,
      rstn => rstn,
      S    => S
      );

  --- reset_gen : process
  --- begin
  ---   rstn <= '0';
  ---   wait for reset_time;
  ---   rstn <= '1';
  ---   wait;
  --- end process reset_gen;

  clock_gen : process
  begin
    loop
      clk <= '0';
      wait for clock_period/2;
      clk <= '1';
      wait for clock_period/2;
    end loop;
  end process clock_gen;

  a_increment : process
  begin
    A <= (others => '0');
    wait for delay;
    loop
      wait for 4*clock_period;
      A <= A + 1;
    end loop;
  end process a_increment;


  stimulus : process
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
  begin
    rstn <= '0';
    ena  <= '0';
    B    <= "00000001";

    wait for reset_time;
    rstn <= '1';

    wait for 10*clock_period;
    ena <= '1';

    wait for 10*clock_period;
    ena <= '0';

    wait for 5*clock_period;
    ena <= '1';

    wait;
  end process stimulus;

end ejemplo_arch;