---------------------------------------------------------
-- registro con enable de ancho de palabra variable
-- 
---------------------------------------------------------

LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY registro IS
GENERIC(
    WIDTH: integer
        );
PORT(
    rstn : IN    STD_LOGIC;
    clk  : IN    STD_LOGIC;
    ena  : IN    STD_LOGIC;
    D    : IN    STD_LOGIC_VECTOR(WIDTH-1 downto 0);
    
    Q    : OUT   STD_LOGIC_VECTOR(WIDTH-1 downto 0)
    );
END registro;

ARCHITECTURE behav OF registro IS
BEGIN
    ---------------
    D_registro:
    ---------------
    PROCESS(clk,rstn,D)  --generacion de los D-FF
        BEGIN
            IF (rstn='0') THEN
                Q <= (OTHERS => '0');
            ELSIF (clk'event AND clk='1') THEN
                IF (ena='1') THEN
                    Q <= D;
                END IF;
            END IF;
    END PROCESS D_registro;
END behav;