------------------------------
-- Package. 
-- 
------------------------------

LIBRARY ieee ;
USE ieee.std_logic_1164.all;

PACKAGE pack_ejemplo is
---Declaración de las constantes utilizadas en el proyecto-------
constant WORD_WIDTH : integer := 8; -- ancho de palabra utilizado
-----------------------------------------------------------------

----------------------------
  component registro
----------------------------
    GENERIC(
        WIDTH: integer
        );
    PORT(
        rstn : IN    STD_LOGIC;
        clk  : IN    STD_LOGIC;
        ena  : IN    STD_LOGIC;
        D    : IN    STD_LOGIC_VECTOR(WIDTH-1 downto 0);
    
        Q    : OUT   STD_LOGIC_VECTOR(WIDTH-1 downto 0)
        );  
  end component;
----------------------------
  component sumador
----------------------------
    GENERIC(
        WIDTH: integer
        );
    PORT(
        A    : IN    STD_LOGIC_VECTOR(WIDTH-1 downto 0);
        B    : IN    STD_LOGIC_VECTOR(WIDTH-1 downto 0);
    
        S    : OUT   STD_LOGIC_VECTOR(WIDTH-1 downto 0)
        );  
  end component;
  
end pack_ejemplo;