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-- version 0 17 Marzo 2002
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LIBRARY ieee ;
library pepe;

USE ieee.std_logic_1164.all;
use pepe.pack_ejemplo.all;

ENTITY ejemplo IS
PORT(
    rstn : IN    STD_LOGIC;
    clk  : IN    STD_LOGIC;
    ena  : IN    STD_LOGIC;
    A    : IN    STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0);
    B    : IN    STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0);

    S    : OUT   STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0)
    );
END ejemplo;

ARCHITECTURE struct OF ejemplo IS

signal  s_A_r  : STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0); --salida de registro donde se almacena A
signal  s_B_r  : STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0); --salida de registro donde se almacena A

BEGIN
---------------
reg_A: registro
---------------
    generic map (
        WIDTH => WORD_WIDTH
        )
    port map (
        --inputs
        rstn  => rstn,
        clk   => clk,
        ena   => ena,
        D     => A,
        --outputs
        Q     => s_A_r
        );
---------------
reg_B: registro
---------------
    generic map (
        WIDTH => WORD_WIDTH
        )
    port map (
        --inputs
        rstn  => rstn,
        clk   => clk,
        ena   => ena,
        D     => B,
        --outputs
        Q     => s_B_r
        );
---------------
Suma_A_B: sumador
---------------
    generic map (
        WIDTH => WORD_WIDTH
        )
    port map (
        --inputs
        A     => s_A_r,
        B     => s_B_r,
        --outputs
        S     => S
        );
END struct;